From 635cfa9d02cff374b1e8cff1493aef178f73cfab Mon Sep 17 00:00:00 2001
From: Malfurious <m@lfurio.us>
Date: Tue, 7 May 2024 04:17:19 -0400
Subject: Add 64-bit ARM architecture constants

Signed-off-by: Malfurious <m@lfurio.us>
---
 architecture.h | 35 +++++++++++++++++++++++++++++++++++
 misplays.c     | 12 ++++++++++++
 2 files changed, 47 insertions(+)

diff --git a/architecture.h b/architecture.h
index 27cec2d..af98ce3 100644
--- a/architecture.h
+++ b/architecture.h
@@ -55,6 +55,41 @@ typedef union {
 #define CAPSTONE_CALL_32        X86_INS_CALL
 #define WORDSIZE_32             4
 
+#elif defined(__aarch64__) || defined(_M_ARM64)
+
+typedef union {
+    struct user_regs_64 {
+        unsigned long long regs[31];
+        unsigned long long sp, pc, pstate;
+    } arm64;
+
+    struct user_regs_32 {
+        unsigned int x;
+    } arm32;
+} user_regs_t;
+
+#define ARCH_AARCH64
+
+#define PROGMCTR_64             arm64.pc
+#define STACKPTR_64             arm64.sp
+#define BREAKPOINT_INSN_64      0xd4200000ul
+#define BREAKPOINT_MASK_64      0xfffffffful
+#define BREAKPOINT_ADJS_64      0x0
+#define CAPSTONE_ARCH_64        CS_ARCH_ARM64
+#define CAPSTONE_MODE_64        CS_MODE_ARM
+#define CAPSTONE_CALL_64        ARM64_INS_BL
+#define WORDSIZE_64             8
+
+#define PROGMCTR_32             arm32.x
+#define STACKPTR_32             arm32.x
+#define BREAKPOINT_INSN_32      0
+#define BREAKPOINT_MASK_32      0
+#define BREAKPOINT_ADJS_32      0
+#define CAPSTONE_ARCH_32        0
+#define CAPSTONE_MODE_32        0
+#define CAPSTONE_CALL_32        0
+#define WORDSIZE_32             4
+
 #else
 #error Detected architecture is not supported!
 #endif
diff --git a/misplays.c b/misplays.c
index 9ae6122..a2535c3 100644
--- a/misplays.c
+++ b/misplays.c
@@ -88,6 +88,18 @@ static void dump_registers(struct thread *dbg, PANEL *pan) {
         pprintw(pan, "rbp = 0x%016llx\n", regs->rbp);
         pprintw(pan, "rip = 0x%016llx\n", regs->rip);
     }
+#elif defined ARCH_AARCH64
+    struct user_regs_64 *regs = &dbg->state->regs.arm64;
+    pprintw(pan, "x0 = 0x%016llx\n", regs->regs[0]);
+    pprintw(pan, "x1 = 0x%016llx\n", regs->regs[1]);
+    pprintw(pan, "x2 = 0x%016llx\n", regs->regs[2]);
+    pprintw(pan, "x3 = 0x%016llx\n", regs->regs[3]);
+    pprintw(pan, "x4 = 0x%016llx\n", regs->regs[4]);
+    pprintw(pan, "x5 = 0x%016llx\n", regs->regs[5]);
+    pprintw(pan, "x6 = 0x%016llx\n", regs->regs[6]);
+    pprintw(pan, "x7 = 0x%016llx\n", regs->regs[7]);
+    pprintw(pan, "sp = 0x%016llx\n", regs->sp);
+    pprintw(pan, "pc = 0x%016llx\n", regs->pc);
 #endif
 }
 
-- 
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